1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and in particular to an electrical fuse rupture circuit of a semiconductor memory apparatus.
2. Related Art
In general, as the degree of integration of a semiconductor memory apparatus sharply increases, tens of millions of memory cells are disposed in one semiconductor memory apparatus. If a failure occurs in even one of these memory cells, the semiconductor memory apparatus cannot perform a desired operation. As a process technology of a semiconductor memory apparatus is developed, failures statistically occur in only a small number of memory cells. When considering manufacturing yield, it is inefficient to discard semiconductor memory devices as bad products due to failures that occur in only a small number of memory cells. In order to cope with this problem, a semiconductor memory apparatus generally has redundant memory cells in addition to normal memory cells. If a failure occurs in a normal memory cell, the failed normal memory cell is replaced with a redundant memory cell. Hereafter, a normal memory cell among the normal memory cells of the device, which should be replaced with a redundant memory cell due to a failure, will be referred to as a ‘memory cell to repair’.
Address information corresponding to the memory cell to repair is provided from a redundancy circuit. The redundancy circuit has a plurality of fuses for programming the address information of the memory cell to repair. Consequently, the redundancy circuit generates address information which is programmed to the fuses; that is, a repair information signal. The semiconductor memory apparatus compares the repair information signal with the address information applied in a read or write operation. When access to the memory cell to repair is attempted, an operation is performed such that access is made to a redundant memory cell instead of the memory cell to repair.
Programming the plurality of fuses provided in the redundancy circuit generally accomplished either by an electrical cutting method or a laser cutting method. The electrical cutting method is a method in which cutting accomplished by applying overcurrent to target fuses, while the laser cutting method is a method in which target fuses requiring cutting are blown using a laser beam. However, the physical fuse programming method using a laser can be performed only at a wafer level, before the semiconductor memory apparatus is manufactured as a package. Consequently, in order to replace a failed memory cell in a packaged state, the electrical cutting method is generally employed rather than the laser cutting method. In other words, in the package state, programming may be performed through changing the connection states of fuses by using the electrical cutting method.
Generally, the electrical cutting method employed in a test of a package is a bit defect (failure) relief technology. In the electrical cutting method employed in the test of the package, it is first determined in which memory cell a bit failure has occurred, overcurrent is applied to the memory cell in which the bit failure has occurred in order to cut the memory cell, and the failed memory cell is replaced with a redundant memory cell to allow current flow.
The operation of cutting the memory cell in which the bit failure has occurred is referred to as an electrical fuse rupture operation. In the conventional art, the electrical fuse rupture operation is performed by applying a specified command from an external controller a predetermined number of times, in order to initiate the electrical fuse rupture operation. After performing the electrical fuse rupture operation the predetermined number of times, it is then determined whether the electrical fuse rupture operation has been properly performed. If an evaluation indicates that the electrical fuse rupture operation has not been properly performed, the electrical fuse rupture operation is initiated once again.
In the case where the external command is repeatedly applied and the result of the electrical fuse rupture operation is repeatedly evaluated, an extended time for package testing results.